1. Field of the Invention
The present invention relates to a semiconductor device whose T-shaped gate is coated with an insulating film, and a method for manufacturing the same. Specifically, the present invention relates to a semiconductor device that suppresses the elevation of capacitance between the gate and the drain to prevent the deterioration of high-frequency characteristics, little fluctuates in the wafer surface, secures high moisture resistance, and can be stably manufactured; and a method for manufacturing such a semiconductor device.
2. Background Art
The generalization of high-frequency semiconductor devices using compound semiconductors, such as GaAs, has been rapidly progressing, and the reduction of costs has been strongly demanded. To respond to such demands, low-cost molded packages have been adopted in place of conventional completely airtight metal packages. However, when a non-airtight package, such as a molded package is used, the high moisture resistance of a semiconductor device is required to prevent deterioration due to moisture.
A method for manufacturing a semiconductor device according to a first conventional embodiment intending the high moisture resistance the semiconductor device will be described referring to the drawings.
First, as shown in FIG. 30, an AlGaAs/GaAs super lattice buffer layer 13, an n-GaAs channel layer 14, an AlGaAs Schottky layer 15, and a GaAs cap layer 16 are sequentially formed as a semiconductor layer 12 on a semi-insulating GaAs substrate 11 using an epitaxial growth process. Si ions are implanted into a predetermined region of the semiconductor layer 12 to form an impurity diffused layer 17, and He ions are implanted to form an element isolating layer (not shown). Then, a SiN film 18 is formed on the semiconductor layer 12 using plasma CVD (chemical vapor deposition).
Next, as shown in FIG. 31, a photo-resist film 21 is applied onto the SiN film 18 to form an opening using lithography. Using the photo-resist film 21 as a mask, the SiN film 18 and the GaAs cap layer 16 are etched by ICP (inductively coupled plasma) to form an opening 22. Thereafter, the photo-resist film 21 is removed. Then, as shown in FIG. 32, a WSi/Au film 23 is formed on the entire surface so as to bury the opening 22 using sputtering.
Next, as shown in FIG. 33, a photo-resist film 24 is applied onto the WSi/Au film 23, and the photo-resist film 24 other than in the vicinity of the opening 22 is removed by lithography. By ion milling using the photo-resist film 24 as a mask, the WSi/Au film 23 is patterned to form a T-shaped gate electrode 25 on the semiconductor layer 12. Thereafter, the photo-resist film 24 is removed.
Next, as shown in FIG. 34, a photo-resist film 26 is applied onto the entire surface, and the photo-resist film 26 on the impurity diffused layer 17 is removed by lithography. Using the photo-resist film 26 as a mask, the SiN film 18 is etched by RIE (reactive ion etching).
Next, as shown in FIG. 35, an AuGe/Ni/Au film is vapor-deposited using vacuum deposition and is subjected to a liftoff process to form a source electrode 27 and a drain electrode 28 ohmic-contacting the impurity diffused layer 17. Then, as shown in FIG. 36, a SiN film 29 is formed on the entire surface so as to coat the T-shaped gate electrode 25.
In the first conventional embodiment as described above, the semiconductor device was protected from corrosion due to moisture by coating the surfaces of the semiconductor layer 12, the T-shaped gate electrode 25 and the like by a thick SiN film 29 formed by plasma CVD or the like. However, when the T-shaped gate electrode 25 was used to prevent the elevation of gate resistance, capacitance components increased because the SiN film 18 having a high dielectric constant was present between the overhanging portion of the T-shaped gate electrode 25 and the semiconductor layer 12, causing a problem of the deterioration of high-frequency characteristics.
A method for manufacturing a semiconductor device according to the second conventional embodiment that solves problems in the first conventional embodiment will be described referring to the drawings.
First, as shown in FIG. 37, in the same manner as in the first embodiment, a semiconductor layer 12 is formed on a semi-insulating GaAs substrate 11, and Si ions are implanted into a predetermined region of the semiconductor layer 12 to form an impurity diffused layer 17. Then, a SiO2 film 19 is formed on the semiconductor layer 12 using plasma CVD.
Next, as shown in FIG. 38, a photo-resist film 21 is applied onto the SiO2 film 19 to form an opening using lithography. Using the photo-resist film 21 as a mask, the SiO2 film 19 and the GaAs cap layer 16 are etched by ICP (inductively coupled plasma) to form an opening 22. Thereafter, the photo-resist film 21 is removed. Then, as shown in FIG. 39, a WSi/Au film 23 is formed on the entire surface so as to bury the opening 22 using sputtering.
Next, as shown in FIG. 40, a photo-resist film 24 is applied onto the WSi/Au film 23, and the photo-resist film 24 other than in the vicinity of the opening 22 is removed by lithography. By ion milling using the photo-resist film 24 as a mask, the WSi/Au film 23 is patterned to form a T-shaped gate electrode 25 on the semiconductor layer 12. Thereafter, the photo-resist film 24 is removed.
Next, as shown in FIG. 41, the SiO2 film 19 is entirely removed using buffered hydrofluoric acid (BHF).
Next, as shown in FIG. 42, a thin SiN film 18 if formed on the entire surface. Then, a photo-resist film 26 is applied onto the entire surface, and the photo-resist film 26 on the impurity diffused layer 17 is removed by lithography. Using the photo-resist film 26 as a mask, the SiN film 18 is etched by RIE.
Next, as shown in FIG. 43, an AuGe/Ni/Au film is vapor-deposited using vacuum deposition and is subjected to a liftoff process to form a source electrode 27 and a drain electrode 28 ohmic-contacting the impurity diffused layer 17.
Then, as shown in FIG. 44, a SiN film 29 having a thickness equal to or larger than the thickness of the T-shaped gate electrode 25 is formed on the entire surface. By thus firming the thick SiN film 29 after forming the T-shaped gate electrode 25, a hollow portion 32 is formed under the spread portion of the T-shaped gate electrode 25. Thereby, the elevation of capacitance between the gate and the drain, which caused problems in the first conventional embodiment, can be prevented.
In the second conventional embodiment, however, since the SiN film 29 enters also under the spread portion of the T-shaped gate electrode 25 to a certain extent, the fluctuation of the capacitance between the gate and the drain in the wafer surface increases. Also depending on the shape and size of the T-shaped gate electrode 25, the hollow portion 32 may not be accurately formed, or a sufficient effect to reduce the capacitance between the gate and the drain may not be obtained. Furthermore, since the SiN film 18 is formed after forming the T-shaped gate electrode 25, the coverage and quality of the SiN film 18 coating the surface of the semiconductor layer 12 under the spread portion of the T-shaped gate electrode 25 are lowered, causing a problem of lowering moisture resistance.
A method for manufacturing a semiconductor device according to the third conventional embodiment that solves problems in the first and second conventional embodiments will be described referring to the drawings (e.g., refer to Japanese Patent Laid-Open No. 11-274175).
First, as shown in FIG. 45, etching is performed to the operative layer of a GaAs substrate 11 using a photo-resist pattern as a mask to form a recess. A SiN film 18 and a SiO2 film 19a are sequentially formed on the GaAs substrate 11. The SiO2 film 19a and the SiN film 18 are processed by dry etching using the photo-resist pattern as a mask to form an opening 22. After forming a metal film on the entire surface so as to bury the opening 22, the metal film is processed by dry etching using the photo-resist pattern as a mask to form a T-shaped gate electrode 25. Further, a SiO2 film 19b is formed on the entire surface to coat the head portion of the T-shaped gate electrode 25.
Next, as shown in FIG. 46, the SiO2 films 19a, 19b and SiN film 18 in regions adjacent to the both ends of the T-shaped gate electrode 25 are selectively removed by wet etching using the photo-resist pattern as a mask. A source electrode 27 and a drain electrode 28 are formed in the opened region by a predetermined method. Thereafter, a SiN film 29 is formed on the entire surface.
Next, as shown in FIG. 47, the SiN film 29 is selectively removed by dry etching using the photo-resist pattern as a mask to form an opening 37 on the T-shaped gate electrode 25. Thereafter, only the SiO2 films 19a and 19b around the T-shaped gate electrode 25 are selectively removed by vapor etching through the opening 37. Next, as shown in FIG. 48, by forming a third SiN film 33 on the entire surface to close the opening 37, a hollow portion 32 is formed around the T-shaped gate electrode 25. Thereby, the elevation of capacitance between the gate and the drain, which caused a problem in the first conventional embodiment, can be suppressed, and the deterioration of high-frequency characteristics can be prevented. Furthermore, the fluctuation in the wafer surface, which caused a problem in the second conventional embodiment, can be reduced, and high moisture resistance can be secured.